BAE Systems Senior Principal SystemVerilog/UVM FPGA Verification Engineer in Austin, Texas

Job Description

-?xml:namespace prefix = "o" /->BAE Systems is experiencing continued growth in our Electro-optic/Infrared/RF markets and we are seeking experienced, highly-motivated Hardware Engineers to join our team. The qualified applicants will experience assignments associated with EO/IR/RF systems, precision pointing, Laser based products or other related technologies at our Austin, Texas location. At BAE Systems we design, develop and manufacture highly sophisticated EO/IR/RF and other electronic solutions that service a variety of product areas for government and commercial applications.

As a Senior Principle SystemVerilog/UVM Verification Engineer at BAE Systems, you will architect and drive the SystemVerilog/UVM methodology on a Project. You will architect a configurable simulation test bench from scratch to simulate and verify complex FPGA designs that include ADC/DAC interfaces, DSP, and high speed SERDES. You will also be expected to develop Universal Verification Components (UVCs) including agents, monitors, scoreboards, etc. You will develop test cases, collect/analyze coverage, run interactive and regression simulations.

A Verification Technical Lead on a given project is expected to drive the methodology, provide assignments and mentor the rest of the verification team, attend all the FPGA VHDL design reviews, facilitate all Verification SV/UVM Design reviews, work with Cost Account Managers to track Schedule and Cost, provide status for all team members, plan and bid future Verification efforts.

You will help innovate the way we use SystemVerilog/UVM, considering reuse. You are expected to understand the systems level design down to the individual FPGAs. You will be working with systems engineers, FPGA designers, and other verification engineers in a fast paced dynamic environment.

Typical Education & Experience

Bachelor's Degree and 12 years work experience or equivalent experience

Required Skills and Education

  • Experience in SystemVerilog/UVM or OVM

  • Experience in Architecting constrained random, self checking testbenches from scratch.

  • Experience in creating Universal Verification Components (agents, monitors, scoreboards) from scratch.

  • Motivated self-starter with leadership skills and ability to effectively work in a team environment

  • Excellent problem solving skills, judgment, and analytical capability, along with follow-up and monitoring skills

  • Strong written and oral presentation skills

  • Ability to attain a DOD security clearance

Preferred Skills and Education

  • Experience as the Technical Lead for a Verification Effort.

  • Digital Signal Processing experience

  • Matlab/Simulink

  • Perl/Python

  • VHDL Design experience

  • Possess an Active DOD Security Clearance

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About BAE Systems Electronic Systems

BAE Systems is a premier global defense and security company with approximately 90,000 employees delivering a full range of products and services for air, land and naval forces, as well as advanced electronics, security, information technology solutions and customer support and services.

The Electronic Systems (ES) sector spans the commercial and defense electronics markets with a broad portfolio of mission-critical electronic systems, including flight and engine controls; electronic warfare and night vision systems; surveillance and reconnaissance sensors; secure networked communications equipment; geospatial imagery intelligence products and systems; mission management; and power-and energy-management systems. Headquartered in Nashua, New Hampshire, ES employs approximately 13,000 people globally, with engineering and manufacturing functions primarily in the United States, United Kingdom, and Israel. Equal Opportunity Employer/Females/Minorities/Veterans/Disabled/Sexual Orientation/Gender Identity/Gender Expression

Senior Principal SystemVerilog/UVM FPGA Verification Engineer


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