BAE Systems Sr Principal SystemVerilog/UVM Verification Engineer in Nashua, New Hampshire

As a Senior Principle FPGA Verification Engineer at BAE Systems, you will use SystemVerilog/UVM to simulate and verify the VHDL FPGA designs of some the defense industry's most complicated systems. In this position, you will be responsible for architecting the SystemVerilog/UVM testbench and running simulations of these systems. You will be using advanced verification methodologies in a mixed language environment interfacing with Matlab models. You are expected to understand the systems level design down to the individual FPGAs. You will be working with systems engineers, designers, and other verification engineers in a fast paced dynamic environment.

Expertise in SystemVerilog/UVM or OVM

Experience in architecting test bench environments for unit and system level verification

Experience in verification using constrained random stimulus in a self-checking environment.

Experience with design and verification tools (Mentor Questa or Cadence).

Digital Signal Processing experience

Matlab/Simulink programming language experience

Perl or Python scripting experience

Sr Principal SystemVerilog/UVM Verification Engineer

Nashua, New Hampshire


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